A random transaction rate (RTR) of a memory device can be an important feature for many applications. While the raw Random Transaction Rate (RTR) of the memory device is determined by the address rate of arrays within the memory device, the total transaction rate of a device is determined by the number of banks in the array and the number of addresses and data word transfers supported by the interface.
One type of memory having a fast RTR is a quad data rate (QDR) static random access memory (SRAM). Conventional QDR SRAMs can support two addresses and data word transfers per interface cycle (i.e., two channels) to access two banks in the array (“QDR-IV”). However, for many applications, conventional QDR SRAM do not provide a desired RTR.
One conventional way to increase RTR can be to embed an SRAM memory into an IC that executes the desired application. However, such approaches may not provide adequate storage for an application, may result in reduced yield for the IC, and/or may add to fabrication complexity and/or cost.